PIC18FxxK42 I2C regiszterei

Beküldte root - p, 01/12/2018 - 10:59

 

 

 

 

 

RxyI2C: I2C PAD Rxy CONTROL REGISTER  (Kat:271 old)
U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
--- SLEW PU<1:0> --- --- TH<1:0>
7.bit 6.bit 5.bit 4.bit 3.bit 2.bit 1.bit 0.bit

 

1-0 bit TH<1:0> : I2C Input Threshold Selection bits
  11 =   SMBus 3.0 (1.35 V) input threshold
  10 =   SMBus 2.0 (2.1 V) input threshold
  01 =   I2C specific input thresholds
  00 =   Standard GPIO Input pull-up, enabled via INLVLxy registers
3-2 bit Unimplemented: Read as ‘0’
5-4 bit PU<1:0>: I2C Pull-up Selection bits
  11 =  Reserved
  10 =  10x current of standard weak pull-up
  01 =  2x current of standard weak pull-up
  00 =  Standard GPIO weak pull-up, enabled via WPUxy bit
6 bit SLEW : I2C specific slew rate limiting is enabled 
  1. =  Standard GPIO Slew Rate; enabled/disabled via SLRxy bit.
  2. = I2C specific slew rate limiting is enabled. Standard pad slew limiting is disabled. The SLRxy bit is ignored. 
    I2C specifikus maximális jelváltozási határ engedélyezve. A szokásos láb jelváltozás nincs engedélyezve. A SLRxy bit nem érvényes.
7 bit Unimplemented: Read as ‘0’

SLEW : I2C specific slew rate limiting is enabled 
1 =I2C specific slew rate limiting is enabled. Standard pad slew limiting is disabled. The SLRxy bit is ignored. 
0 = Standard GPIO Slew Rate; enabled/disabled via SLRxy bit.

Adatlap: Itt
I2C kommunikáció (Eng.): Itt

 
Regiszter 7. bit 6. bit 5. bit 4. bit 3. bit 2. bit 1. bit 0. bit info
doksi
I2CxBTO — — — — — BTO<2:0>
R/W-0/0		 582
I2CxCLK — — — — BLK<3:0>
R/W-0/0		 581
I2CxPIE CNTIE
R/W-0		 ACKTIE
R/W-0		 —
U=0		 WRIE
R/W-0		 ADRIE
R/W-0		 PCIE
R/W-0		 RSCIE
R/W-0		 SCIE
R/W-0		 588
PIE2 I2C1RXIE SPI1IE SPI1TXIE SPI1RXIE DMA1AIE DMA1ORIE DMA1DCNTIE DMA1SCNTIE 149
PIE3 TMR0IE U1IE U1EIE U1TXIE U1RXIE I2C1EIE I2C1IE I2C1TXIE 150
PIE5 I2C2TXIE I2C2RXIE DMA2AIE DMA2ORIE DMA2DCNTIE DMA2SCNTIE C2IE INT1IE 152
PIE6 TMR3GIE TMR3IE U2IE U2EIE U2TXIE U2RXIE I2C2EIE I2C2IE 153
I2CxPIR CNTIF
R/W/HS-0		 ACKTIF
R/W/HS-0		 —
U-0		 WRIF
R/W/HS-0		 ADRIF
R/W/HS-0		 PCIF
R/W/HS-0		 RSCIF
R/W/HS-0		 SCIF
R/W/HS-0		 587
PIR2 I2C1RXIF SPI1IF SPI1TXIF SPI1RXIF DMA1AIF DMA1ORIF DMA1DCNTIF DMA1SCNTIF 139
PIR3 TMR0IF U1IF U1EIF U1TXIF U1RXIF I2C1EIF I2C1IF I2C1TXIF 140
PIR5 I2C2TXIF I2C2RXIF DMA2AIF DMA2ORIF DMA2DCNTIF DMA2SCNTIF C2IF INT1IF 142
PIR6 TMR3GIF TMR3IF U2IF U2EIF U2TXIF U2RXIF I2C2EIF I2C2IF 143
PMD5 — — U2MD U1MD — SPI1MD I2C2MD I2C1MD 295
I2CxERR -—
U-0		 BTOIF
R/W/HS-0		 BCLIF
R/W/HS-0		 NACKIF
R/W/HS-0		 —
U-0		 BTOIE
R/W-0		 BCLIE
R/W-0		 NACKIE
R/W-0		 585
I2CxSTAT0 BFRE
R-0		 SMA
R-0		 MMA
R-0		 R
R-0		 D
R-0		 —
U-0		 —
U-0		 —
U-0		 583
I2CxSTAT1 TXWE
R/W/HS-0		 —
U-0		 TXBE
R-1		 —
U-0		 RXRE
R/W/HS-0		 CLRBF
R/S-0/0		 —
U-0		 RXBF
R-0		 584
I2CxCON0 EN
R/W-0		 RSEN
R/W-0		 S
R/W/HC/HS-0		 CSTR
R/C/HS/HC-0		 MDR
R-0		 MODE<2:0>
R/W-0		 577
I2CxCON1 ACKCNT
R/W-0		 ACKDT
R/W-0		 ACKSTAT
R-0		 ACKT
R-0		 —
U-0		 RXOV
R/W/HC/HS-0		 TXU
R/W/HC/HS-0		 CSD
R/W-0		 579
I2CxCON2 ACNT
R/W-0		 GCEN
R/W-0		 FME
R/W-0		 ADB
R/W-0		 SDAHT<3:2>
R/W-0		 BFRET<1:0>
R/W-0		 580
I2CxADR0 ADR<7:0>
R/W-1		 589
I2CxADR1 ADR<7:1>
R/W-1		 —
U-0		 590
I2CxADR2 ADR<7:0>
R/W-1		 591
I2CxADR3 ADR<7:1>
R/W-1		 — 592
I2CxADB0 ADB<7:0> 593
I2CxADB1 ADB<7:0> 594
I2CxCNT CNT<7:0> 586
I2CxRXB RXB<7:0>  
I2CxTXB TXB<7:0>  
I2CxSDAPPS — — — I2CxSDAPPS<4:0> 277
I2CxSCLPPS — — — I2CxSCLPPS<4:0> 277
xxxPPS     xxxPPS<5:0>
R/W-m/u		 277
RxyI2C —
U-0		 SLEW
R/W-0/0		 PU<1:0>
R/W-0/0		 —
U-0		 —
U-0		 TH<1:0>
R/W-0/0		 271
                   
                   
 

 

 

 
     

BTO<2:0>
I2CxBTO		 BTO<2:0> (R/W-0/0): I2C Bus Timeout Selection bits

I2C Busz időtúllépés kiválasztó bitek
 
BTO<2:0>  I2Cx Bus időtúllépés választó bitek
111 CLC4OUT
110 CLC3OUT
101 CLC2OUT
100 CLC1OUT
011 TMR6 post scaled output
010 TMR4 post scaled output
001 TMR2 post scaled output
000 Foglalt, fenntartott

Vissza		 BTO<2:0>: I2C Bus Timeout Selection bits
 
BTO<2:0>  I2Cx Bus Timeout Selection
111 CLC4OUT
110 CLC3OUT
101 CLC2OUT
100 CLC1OUT
011 TMR6 post scaled output
010 TMR4 post scaled output
001 TMR2 post scaled output
000 Reserved

Vissza

I2CxCLK		 BTO  (R/W-0/0):  I2C BUS TIMEOUT SELECTION REGISTER/
I2C busz időtúllépést mérő jelforrást választó regiszter
I2C busz időtúllépést mérő jelforrást választó regiszter
 
BTO<3:0>  I2Cx Órajel választás
1010-1111 Fenntartott
1001 SMT1túlcsordulás
1000 TMR6 post scaled kimenet
0111 TMR4 post scaled kimenet
0110 TMR2 post scaled kimenet
0101 TMR0 túlcsordulás (időlefutás)
0100 Clock Reference output
0011 MFINTOSC (500 kHz)
0010 HFINTOSC (Belső nagysebességű oszcillátor)
0001 Fosc (CPU órajel)
0000 Fosf/4 (CPU órajel/4)

Vissza		  I2C BUS TIMEOUT SELECTION REGISTER


 
CLK<3:0>  I2Cx Clock Selection
1010-1111 Reserved
1001 SMT1 overfow
1000 TMR6 post scaled output
0111 TMR4 post scaled output
0110 TMR2 post scaled output
0101 TMR0 overflow
0100 Clock Reference output
0011 MFINTOSC (500 kHz)
0010 HFINTOSC 
0001 Fosc
0000 Fosf/4

Vissza

I2CxPIE

<SCIE>
<RSCIE>
<PCIE>
<ADRIE>
<WRIE>
<--->
<ACKTIE>
<CNTIE>		 I2CxPIE: I2CxIE INTERRUPT AND HOLD ENABLE REGISTER
I2CxIE megszakítás és HOLD (tartás) engedélyező regiszter

 SCIE (R/W-0) (0.bit) Indítási állapotban a megszakítás engedélyezése
  1. Indulás érzékelésekor ne szakítson meg
  2. Indítás érzékelésekor is engedélyezi a megszakítást
RSCIE (R/W-0) (1.bit): Újraidítási állapotban a megszakítás engedélyezése
  1. Indulás érzékelésekor ne szakítson meg
  2. Újraindítás érzékelésekor is engedélyezi a megszakítást
PCIE (R/W-0) (2.bit): Stop állapotban a megszakítás engedélyezése
  1. Stop érzékelésekor nincs engedélyezve a megszakítás
  2. Engedélyezi a megszakítász Stop érzékelésekor is
ADRIE (R/W-0) (3.bit):Címzéskor a megszakítása és tartást engedélyező bit
  1. Címzés közben nincs engedélyezve a megszakítás és a tartás
  2. Ha  ADRIF=1, CSTR=1 csak akkor engedélyezett a megszakítás
WRIE (R/W-0) (4.bit): Adat íráskor a megszakítást és megtartást engedélyező bit
  1. Adat íráskor nincs engedélyezve a megszakítás és megtartás (folytatáshoz)
  2. csak ha  WRIF=1; CSTR=1
--- (5.bit)
ACKTIE (R/W-0) (6.bit): Acknowledge (Time) Interrupt and Hold Enable bit
Az ACK, NACK-kor és erre szánt idő alatt a megszakítás engedélyezése
  1. A nyugtázáskor és az erre adott idő alatt nincs engedélyezve a megszakítás
  2.  Ha ACKTIF=1 akkor:
    Ha az ACK jel van vagy volt és még a CSTR=1
    Ha a  NACK jel van vagy volt, és CSTR változatlan
    Vagyis az ACK-nak vagy NACK-nak szánt idő alatt engedélyezve van a megszakítás
CNTIE (R/W-0) (7.bit): Byte Count (Time) Interrupt Enable bit
Bájtok számolása idején a megszakítást engedélyező bit
  1. CNTIE: Byte Count Interrupt Enable bit
  2. Ha I2CxPIR regiszterben CNTIF=1
Megjehyzés 1: Enabled interrupt flags are OR’d to produce the PIRx<I2CxIF> bit.		 I2CxPIE: I2CxIE INTERRUPT AND HOLD ENABLE REGISTER

 SCIE (0.bit) Start Condition Interrupt Enable
  1. Start detection interrupts are disabled
  2. Enable interrupt on detection of Start condition
     
RSCIE (1.bit): Restart Condition Interrupt Enable
  1. Start detection interrupts are disabled
  2. Enable interrupt on detection of Restart condition
     
PCIE (2.bit): Stop Condition Interrupt Enable
  1. Stop detection interrupts are disabled
  2. Enable interrupt on detection of Stop condition
     
ADRIE (3.bit): Address Interrupt and Hold Enable bit
  1. Address holding and interrupt is disabled
  2. When ADRIF is set; CSTR is set


     
WRIE (4.bit): Data Write Interrupt and Hold Enable bit
  1. Data Write holding and interrupt is disabled
  2. When WRIF is set; CSTR is set

     
--- (5.bit)
ACKTIE (6.bit): Acknowledge Interrupt and Hold Enable bit
  1. Acknowledge holding and interrupt is disabled
  2.  When ACKTIF is set
    If ACK is generated, CSTR is also set.
    If NACK is generated, CSTR is unchanged




     
CNTIE (7.bit): Byte Count Interrupt Enable bit
  1. CNTIE: Byte Count Interrupt Enable bit
  2. When CNTIF is set
Note 1:Enabled interrupt flags are OR’d to produce the PIRx<I2CxIF> bit.
 
 Vissza

I2CxPIR

<SCIF>
<RSCIF>
<PCIF>
<ADRIF>
<WRIF>
<--->
<ACKTIF>
<CNTIF>		 I2CxPIR: I2CxIF (PERIPHERY) INTERRUPT FLAG REGISTER
SCIF (R/W/HS-0) (0.bit): Start Condition Interrupt Flag
Start állapot megtörténtét érzékelő megszakítésjelző bit
  1. Nem történt START állapot
  2. Történt START állapot
RSCIF (R/W/HS-0) (1.bit): Restart Condition Interrupt Flag
Restart állapot megtörténtét érzékelő megszakítésjelző bit
  1. RESTART állapotot nem történt
  2. RESTART állapotot (jelet) érzékelt
PCIF (R/W/HS-0) (2.bit): Stop Condition Interrupt Flag
Stop állapot megtörténtét érzékelő megszakítésjelző bit
  1. A STOP állapotot nem történt
  2.  STOP állapotot (jelet) érzékelt 
ADRIF (R/W/HS-0) (3.bit): Address Interrupt Flag bit (MODE<2:0> = 0xx OR 11x)
A címzés megtörténtét jelző megszakításbit. Ez a mesterre vonatkozik.
  1. Nem történt meg a címzés kiküldése
  2. 1-re áll, ha kiment a megcímzés a 8. órajel lefutó élénél. A 10 bites címzésnél ez kétszer történik meg, de szerintem nekünk kell a bitet visszaállítani 0-ra
WRIF (R/W/HS-0) (4.bit): Data Write Interrupt Flag bit (MODE<2:0> = 0xx OR 11x)
Adatküldés megtörténtét jelző megszakítás bit  Ez a mesterre vonatkozik.
  1. Nem történt adatküldés
  2. 1-re áll, ha megtörtént az adatküldés a 8. órajel lefutó élénél. Gondolom, hogy nekünk kell visszaállítani és így minden kiküldött bájtnál tud jelezni.
--- (5.bit) Unimplemented: Read as ‘0’.
ACKTIF (R/W/HS-0) (6.bit): Acknowledge Status Time Interrupt Flag bit(2) (MODE<2:0> = 0xx OR 11x)
ACK jel megvalósulását jelző megszakításbit. Ez a mesterre vonatkozik. 
  1. ACK jel (nyugtázás) nem történt
  2. 1-re áll, ha megtörtént az ACK jel, vagyis a nyugtásás, mégpedig a 9. szinkronjel lefutó élénél.
    Megj.: Azt nem tudom, hogy ez a szolgától fogadott adatra, vagy a mester által kiküldött adtra a szolga nyugtázó jelére vonatkozik-e, vagy esetleg mindkettőre.
    Gondolom, hogy nekünk kell visszaállítani és így minden ACK jelnél tud jelezni.
    KI KELL MAJD PRÓBÁLNI!
CNTIF (R/W/HS-0) (7.bit): Byte Count Interrupt Flag bit
A küldött/fogadott adatbájtok számát figyeli vagy nem figyeli, és ha  eléri az általunk az I2CxCNT-ben megadott értéket, akkor jelezhet ez a megszakítás bit.
  1. I2CCNT állapotát nem figyeli
  2. Ha I2CCNT = 0, akkor a 9. szinkronjel lefutó élénél -re vált.
  1. Note:
    Enabled interrupt flags are OR’d to produce the PIRx<I2CxIF> bit.
  2.  Note:
    ACKTIF is not set by a matching, 10-bit, high address byte with the R/W bit clear. It is only set after the matching low address byte is shifted in.
 I2CxPIR: I2CxIF INTERRUPT FLAG REGISTER

SCIF (0.bit): Start Condition Interrupt Flag
  1. No Start condition detected
  2. Set on detection of Start condition
RSCIF (1.bit): Restart Condition Interrupt Flag
  1. No Restart condition detected
  2. Set on detection of Restart condition
     
PCIF (2.bit): Stop Condition Interrupt Flag
  1. No Stop condition detected
  2. Set on detection of Stop condition
     
ADRIF(3.bit): Address Interrupt Flag bit (MODE<2:0> = 0xx OR 11x)
  1. Address condition not detected
  2. Set the 8th falling edge of SCL for a matching received (high/low) address byte

     
WRIF (4.bit): Data Write Interrupt Flag bit (MODE<2:0> = 0xx OR 11x)
  1. Data Write condition not detected
  2. Set the 8th falling edge of SCL for a received data byte

     
--- (5.bit) Unimplemented: Read as ‘0’.
ACKTIF (6.bit): Acknowledge Status Time Interrupt Flag bit(2) (MODE<2:0> = 0xx OR 11x)
  1. Acknowledge condition not detected
  2. Set by the 9th falling edge of SCL for any byte when addressed as a Slave






     
CNTIF (7.bit): Byte Count Interrupt Flag bit
  1. I2CCNT condition has not occurred
  2. When I2CCNT = 0, set by the 9th falling edge of SCL
  1. Note:
    Enabled interrupt flags are OR’d to produce the PIRx<I2CxIF> bit.
  2.  Note:
    ACKTIF is not set by a matching, 10-bit, high address byte with the R/W bit clear. It is only set after the matching low address byte is shifted in.

I2CxERR

<NACKIE>
<BCLIE>
<BTOIE>
<--->
<NACKIF>
<BCLIF>
<BTOIF>
<--->		 I2CxERR: I2C ERROR REGISTER

 NACKIE (R/W-0) (0bit): NACK jelet érzékelésének és megszakítás genetálását engebélyző bit beállítása.
Megj.: A NACK jelet a mester adja ki, ha sikerült neki fogadni a szolga által küldött adatokat, és a szolga érzékeli ezt, példáuk, hogy további adatokat küldjön.
  1. NACKIF-nek nincs engedélyezve a megszakítás
  2. Engedélyezve a megszakítás ha NACKIF 1-re vált.
BCLIE (R/W-0) (1.bit): Busz ütközés esetén a megszakítást engedélyező bit beállítása
  1. Busz ütközés esetén nincs engedélyezve a megszakítás
  2. Engedélyezve a megszakítás busz ütközés esetén. Ha BCLIF=1.
BTOIE (R/W-0) (2.bit): Bus Time-Out Interrupt Enable bit
  1. Bus Tim-out not enabled
  2. Enable interrupt on bus time out
--- (3.bit)
NACKIF (R/W/HS-0) (4.bit): NACK jelet érzékelő megszakításjelző bit mit váltson ki?(1)
  1. No NACK/Error detected
    NACKIF is not set by the NACK send for non-matching slave addresses
  2.  When (SMA = 1 || MMA = 1) and a NACK is detected on the bus NACKIF is also set when any of the TXWRE, RXRDE, TXUF, RXOVR bits are set.

BCLIF (R/W/HS-0) (5.bit): Bus Collision Detect Interrupt Flag bit(1)
  1. No bus collision detected
  2.  Bus collision detected (On the rising edge of SCL input, SDA output is high and input is sampled low) Slave and Master Mode the module immediately goes idle Multi-Master Mode attempts to match slave addresses, and/or goes idle
BTOIF (R/W/HS-0) (6.bit): Bus Time-Out Interrupt Flag bit(1,2)
  1. No bus timeout
  2.  Bus Timeout occurred 
--- (7.bit)
  1. Note: Enabled error interrupt flags are OR’d to produce the PIRx<I2CEIF> bit.
  2. Note: User software must select the Bus Time-out Source in the I2CBTO register.
     
 		 I2CxERR: I2C ERROR REGISTER

 NACKIE (0bit): NACK Detect Interrupt Enable bit
  1. NACKIF interrupt is disabled
  2. Enable interrupt on NACKIF


     
BCLIE (1.bit): Bus Collision Detect Interrupt Enable bit
  1. Bus collision interrupts are disabled
  2. Enable interrupt on bus collision
BTOIE (2.bit): Bus Time-Out Interrupt Enable bit
  1. Bus Tim-out not enabled
  2. Enable interrupt on bus time out
--- (3.bit)
NACKIF (4.bit): NACK Detect Interrupt Flag bit(1)
  1. No NACK/Error detected
    NACKIF is not set by the NACK send for non-matching slave addresses
  2.  When (SMA = 1 || MMA = 1) and a NACK is detected on the bus NACKIF is also set when any of the TXWRE, RXRDE, TXUF, RXOVR bits are set.

BCLIF (5.bit): Bus Collision Detect Interrupt Flag bit(1)
  1. No bus collision detected
  2.  Bus collision detected (On the rising edge of SCL input, SDA output is high and input is sampled low) Slave and Master Mode the module immediately goes idle Multi-Master Mode attempts to match slave addresses, and/or goes idle
BTOIF (6.bit): Bus Time-Out Interrupt Flag bit(1,2)
  1. No bus timeout
  2.  Bus Timeout occurred 
--- (7.bit)
  1. Note: Enabled error interrupt flags are OR’d to produce the PIRx<I2CEIF> bit.
  2. Note: User software must select the Bus Time-out Source in the I2CBTO register.
     
 

I2CxSTAT0


I2CxSTAT0: I2C STATUS REGISTER 0
--- (0-2.bit)
D (R-0) (3.bit): Data bit
  1. Jelzi, hogy az utolsó fogadott vagy továbbított bájt adat volt
  2. Jelzi, hogy a fogadott vagy továbbított utolsó bájt nem adat, hanem cím volt.
R(R-0) (4.bit): Read Information bit(1,2)
  1. Azt jelzi, hogy a fogadott utolsó egyező (magas) címen írási kérés volt
  2. Azt jelzi, hogy az utolsó egyeztetett (magas) cím olvasási kérés volt
MMA(R-0) (5.bit): Master Module Active Status bit
  A mester modul aktív státuszát jelző bit
  1. Master state machine is idle
    0, ha  BCLIF=1.
    0, ha a mester kiadta az adatvonalra a STOP jelet.
    Cleared for BTOIF condition, after the master
    successfully shifts out a Stop condition.
  2. Master üzemmód aktív.
    Set when master state machine asserts a Start on bus
SMA(R-0) (6.bit): Slave Module Active Status bit
  Szolga üzemmódot jelző bit
  1. Törlődik, ha a buszon RESTART-ot vagy STOP-ot érzékel
  2. 1, ha a 8. órajel után az eddigre beérkezett cím megegyezik a saját 7 bites címével.

    Set after the 8th falling SCL edge of a received matching 10-bit slave low address
    Set after the 8th falling SCL edge of a received matching 10-bit slave high w/ read address, only
    after a previous matching high and low w/ write.
BFRE(R-0) (7): Bus Free Status bit(3)
  1. Bus not idle (Ha nincs az I2CCLK regiszterben megadva at ójalt forrása megadva, akkor is 0-t jelez a bit)
  2. Indicates the I2C bus is idle
    Both SCL and SDA have been high for time-out selected by I2CCON2<BFRET<1:0>> bits.
    I2CCLK must select a valid clock source for this bit to function.
 
  1. Note: This bit holds the R bit information following the last received address match. Addresses transmitted by the Master or appearing on the bus without a match do not affect this bit.
  2. Note: Clock requests and input from I2CxCLK register are disabled in Slave modes.
  3. Note: Software must use the EN bit to force Master or Slave hardware to idle.




 		 I2CxSTAT0: I2C STATUS REGISTER 0
--- (0-2.bit)
D (3.bit): Data bit
  1. Indicates the last byte received or transmitted was data
  2. Indicates the last byte received or transmitted was an address
R (4.bit): Read Information bit(1,2)
  1. Indicates the last matching received (high) address was a Write
  2. Indicates the last matching received (high) address was a Read request
MMA (5.bit): Master Module Active Status bit
  1. Master state machine is idle
    Cleared when BCLIF is set
    Cleared when Stop is shifted out by master.
    Cleared for BTOIF condition, after the master
    successfully shifts out a Stop condition.
  2. Master Mode state machine is active
    Set when master state machine asserts a Start on bus
SMA (6.bit): Slave Module Active Status bit
  1. Cleared by any Restart/Stop detected on the bus
    Cleared by BTOIF and BCLIF conditions
  2. Set after the 8th falling SCL edge of a received matching 7-bit slave address
    Set after the 8th falling SCL edge of a received matching 10-bit slave low address
    Set after the 8th falling SCL edge of a received matching 10-bit slave high w/ read address, only
    after a previous matching high and low w/ write.
BFRE (7): Bus Free Status bit(3)
  1. Bus not idle (When no I2CCLK is selected, this bit remains clear)
  2. Indicates the I2C bus is idle
    Both SCL and SDA have been high for time-out selected by I2CCON2<BFRET<1:0>> bits.
    I2CCLK must select a valid clock source for this bit to function.
 
  1. Note: This bit holds the R bit information following the last received address match. Addresses transmitted by the Master or appearing on the bus without a match do not affect this bit.
  2. Note: Clock requests and input from I2CxCLK register are disabled in Slave modes.
  3. Note: Software must use the EN bit to force Master or Slave hardware to idle.
 
 
 

I2CxSTAT1
I2CxSTAT1: I2C STATUS REGISTER 1

 RXBF(R-0) (0.bit): Receive Buffer Full Status bit
A vett adat térolóregiszterének éllapotát jelző bitt. Adatfogadáskor ezt a bitet figyeljük, ha 1, akkor kiolvassuk az adatot, ha újból 1, akkor a következő adatot is kiolvassuk, és így tovább.
  1. I2CRXB (a vett adat tárolója) üres
  2. I2CRXB fogadott új adattal fel van töltődve. Az RXBF bit törlődik ha kiolvassuk az I2CRXB regisztert, és azI2CRXB is kész az esetleges új vett adatot betárolni
--- (1.bit)
CLRBF (R/S-0/0) (2.bit): Clear Buffer bit
  • A bit beállítása törli/kiüríti a fogadási és továbbítási puffereket, ami az RXBF és a TXBE visszaállítását okozza. A bit beállítása törli az RXIF és a TXIF megszakítási bitekez. Ez a bit csak speciális funkció, és mindig '0'
RXRE (R/W/HS-0) (3.bit): Receive Read Error Status bit
  1. No receive overflow
  2. A byte of data was read from I2CxRXB when it was empty. (Must be cleared by software)
--- (4.bit)
TXBE (R-1) (5.bit): Transmit Buffer Empty Status bit
  1. I2CTXB is full
  2. I2CTXB is empty (Cleared by writing the I2CTXB register)
--- (6.bit)
TXWE (R/W/HS-0) (7.bit): Transmit Write Error Status bit(2)
  1. No transmit write error
  2. A new byte of data was written to I2CTXB when it was full (Must be cleared by software)
  1. Note: The bits are held in Reset when I2CEN = 0.
  2. Note: Will cause NACK to be sent for slave address and master/slave data read bytes.
  3. Note: Used as triggers for DMA operation.


 
I2CxSTAT1: I2C STATUS REGISTER 1

 RXBF (0.bit): Receive Buffer Full Status bit
 
  1. I2CRXB is empty
  2. I2CRXB has received new data (Cleared by reading the I2CRXB register)


     
--- (1.bit)
CLRBF (2.bit): Clear Buffer bit
  • Setting this bit clears/empties the receive and transmit buffers, causing reset of RXBF and TXBE. Setting this bit clears the RXIF and TXIF interrupt flags. This bit is set-only special function, and always reads ‘0’
 
RXRE (3.bit): Receive Read Error Status bit
  1. No receive overflow
  2. A byte of data was read from I2CxRXB when it was empty. (Must be cleared by software)
--- (4.bit)
TXBE (5.bit): Transmit Buffer Empty Status bit
  1. I2CTXB is full
  2. I2CTXB is empty (Cleared by writing the I2CTXB register)
--- (6.bit)
TXWE (7.bit): Transmit Write Error Status bit(2)
  1. No transmit write error
  2. A new byte of data was written to I2CTXB when it was full (Must be cleared by software)
  1. Note: The bits are held in Reset when I2CEN = 0.
  2. Note: Will cause NACK to be sent for slave address and master/slave data read bytes.
  3. Note: Used as triggers for DMA operation.
 

 

I2CxCON0
I2CxCON0: I2C CONTROL REGISTER 0

MODE<2:0> (R/W-0) (0-2bit): I2C Mode Select bits


 
MODE<2:0> I2C Mode Select bits
 
111 I2C Muti-Master mode (SMBus 2.0 Host),(5)
Works as both mode<2:0> = 001 and mode<2:0> = 100
110 I2C Muti-Master mode (SMBus 2.0 Host),(5)
Works as both mode<2:0> = 000 and mode<2:0> = 100
101 I2C Master mode, 10-bit address
100 I2C Master mode, 7-bit address
011 I2C Slave mode, one 10-bit address with masking
010 I2C Slave mode, two 10-bit address
001 I2C Slave mode, one 7-bit address with masking
000 I2C Slave mode, two 7-bit address

Vissza
 
MDR (R-0) (3.bit): Master Data Request (Master pause)
  1. Master clocking of data is enabled.
  2. Master state mechine pauses until data is read/written to proceed (SCL is output held low)

    MMA = 1 & RXBF = 1
    pause_for_rx - Set by hardware on 7th falling SCL edge
    - User must read from I2CRXB to release SCL
    MMA = 1 & TXBE = 1 & I2CCNT!= 0
    pause_for_tx - Set by hardware on 8th falling SCL edge
    - User must write to I2CTXB to release SCL
    ADB = 1
    - I2CCNT is ignored for the high and low address in 10-bit mode pause_for_restart - Set by hardware on 9th falling SCL edge
    RSEN = 1 & MMA = 1 && I2CCNT = 0 || ACKSTAT = 1
    - User must set START or write to I2CTXB to release SCL and shift Restart onto bus

CSTR (R/C/HS/HC-0) (4.bit): Slave Clock Stretching bit(3)
  1. Enable clocking, SCL control is released
  2. Clock is held low (clock stretching)

    SMA = 1 and RXBF = 1(6)
    - Set by hardware on 7th falling SCL edge
    - User must read byte I2CRXB to release SCL
    SMA = 1 and TXBE = 1 and I2CCNT!= 0
    - Set by hardware on 8th falling SCL edge
    - User must write byte to I2CTXB to release SCL
    when ADRIE is set(4)
    -Set by hardware on 8th falling SCL edge of matching received address
    - User must clear CSTR to release SCL
    SMA = 1 & WRIE = 1
    -Set by hardware on 8th falling SCL edge of received data byte
    - User must clear CSTR to release SCL
    SMA = 1 & ACKTIE = 1
    - Set by hardware on 9th falling SCL edge
    - User must clear CSTR to release SCL

     


S (R/C/HS/HC-0) (5.bit): Master Start/Restart bit (Only Mode<2:0> = 1xx)

When MMA = 0

  1. = Cleared by hardware after sending Start
  2. = Set by user set of START bit or write to I2CTXB, waits for BFRE = 1 to begin with a Start

When (MMA = 1 & MDR = 1 & pause_for_Restart)

  1. = Cleared by hardware after sending Restart
  2. = Set by user set of START bit or write to I2CTXB, resumes communication with a Restart
Else - Writes to I2CTXB or set has no effect on Start bit


 
RSEN (R/W-0) (6.bit): Restart Enable bit (Only mode<2:0> = 1xx)
  1. When (I2CCNT = 0 or ACKSTAT = 1), on 9th falling SCL; master shifts out a Stop condition
  2.  When (I2CCNT = 0 or ACKSTAT = 1), on 9th falling SCL sets MDR
EN (R/W-0) (7.bit): I2C Module Enable bit
   I2C modul engedélyezése, vagyis bekapcsolása
  1. Nincs bekepcsolva az I2C module.
  2. Be van kapcsolva I2C modul(1,2)
Note :
  1. Note: SDA és  SCL  lábakat nyitott kollektoros meghajtásúra kell konfigurálni és a belső felhúzó elleneállásokat be kell kapcsolni vagy ha nem, akkor meg küldő felhúzó ellenállásokat kerll alkalmazni mindkét lábon. A felhúzás többnyire a pozitív tápfeszültségre történik (belsővel mindig), aminek az erősségét a belső ellenállásokkal is lehet szabályozni, ami gyorsabb adatsebesség esetén kisebb ellenállásúnak  kell lenni.
     
  2. SDA és SCL lábakat össze kell rendelni az I2Cx modulhoz oda-vissza alapon, így két regiszterrel kell elvégezni (SSP). Megj.:  Ehhez unlockolni kell és speciális kódokat kell használni, majd lockolni kell.
     
  3. A CSTR-rel egynél több hardverforrással is beállítható, az összes forrást a felhasználói szoftvernek kell kezelnie, mielőtt az SCL vonalat (szinkronjelet) kiadja. A CSTR egy modul státuszbit, és nem mutatja az igazi buszállapotot.
     
  4. SMA is set on the same SCL edge as CSTR for a matching received address
     Az SMA ugyanazon az SCL élen van beállítva, mint a CSTR egy megfelelő fogadott címmel
     
  5. In this mode, ADRIE should be set, this allows an interrupt to clear the BCLIF condition and allow the ACK of matching address.
    Ebben a módban az ADRIE-t kell beállítani, ez lehetővé teszi a megszakításnak a BCLIF feltétel törlését, és lehetővé teszi a megfelelő cím ACK-jét.
     
  6. In 10-bit Slave mode, when ADB = 1, CSTR will set when the high address has not been read out of I2CxRXB before the low address is shifted in. 
    A 10-bites slave módban, ha ADB = 1, CSTR lesz beállítva, amikor a magas címet nem kiolvasott I2CxRXB előtt az alacsony cím eltolt.


 		 I2CxCON0: I2C CONTROL REGISTER 0

MODE<2:0> (0-2bit): I2C Mode Select bits


 
MODE<2:0> I2C Mode Select bits
 
111 I2C Muti-Master mode (SMBus 2.0 Host),(5)
Works as both mode<2:0> = 001 and mode<2:0> = 100
110 I2C Muti-Master mode (SMBus 2.0 Host),(5)
Works as both mode<2:0> = 000 and mode<2:0> = 100
101 I2C Master mode, 10-bit address
100 I2C Master mode, 7-bit address
011 I2C Slave mode, one 10-bit address with masking
010 I2C Slave mode, two 10-bit address
001 I2C Slave mode, one 7-bit address with masking
000 I2C Slave mode, two 7-bit address

Vissza
 
MDR (3.bit): Master Data Request (Master pause)
  1. Master clocking of data is enabled.
  2. Master state mechine pauses until data is read/written to proceed (SCL is output held low)

    MMA = 1 & RXBF = 1
    pause_for_rx - Set by hardware on 7th falling SCL edge
    - User must read from I2CRXB to release SCL
    MMA = 1 & TXBE = 1 & I2CCNT!= 0
    pause_for_tx - Set by hardware on 8th falling SCL edge
    - User must write to I2CTXB to release SCL
    ADB = 1
    - I2CCNT is ignored for the high and low address in 10-bit mode pause_for_restart - Set by hardware on 9th falling SCL edge
    RSEN = 1 & MMA = 1 && I2CCNT = 0 || ACKSTAT = 1
    - User must set START or write to I2CTXB to release SCL and shift Restart onto bus

CSTR (4.bit): Slave Clock Stretching bit(3)
  1. Enable clocking, SCL control is released
  2. Clock is held low (clock stretching)

    SMA = 1 and RXBF = 1(6)
    - Set by hardware on 7th falling SCL edge
    - User must read byte I2CRXB to release SCL
    SMA = 1 and TXBE = 1 and I2CCNT!= 0
    - Set by hardware on 8th falling SCL edge
    - User must write byte to I2CTXB to release SCL
    when ADRIE is set(4)
    -Set by hardware on 8th falling SCL edge of matching received address
    - User must clear CSTR to release SCL
    SMA = 1 & WRIE = 1
    -Set by hardware on 8th falling SCL edge of received data byte
    - User must clear CSTR to release SCL
    SMA = 1 & ACKTIE = 1
    - Set by hardware on 9th falling SCL edge
    - User must clear CSTR to release SCL

     


S (5.bit): Master Start/Restart bit (Only Mode<2:0> = 1xx)

When MMA = 0

  1. = Cleared by hardware after sending Start
  2. = Set by user set of START bit or write to I2CTXB, waits for BFRE = 1 to begin with a Start

When (MMA = 1 & MDR = 1 & pause_for_Restart)

  1. = Cleared by hardware after sending Restart
  2. = Set by user set of START bit or write to I2CTXB, resumes communication with a Restart
Else - Writes to I2CTXB or set has no effect on Start bit


 
RSEN (6.bit): Restart Enable bit (Only mode<2:0> = 1xx)
  1. When (I2CCNT = 0 or ACKSTAT = 1), on 9th falling SCL; master shifts out a Stop condition
  2.  When (I2CCNT = 0 or ACKSTAT = 1), on 9th falling SCL sets MDR
EN (7.bit): I2C Module Enable bit
  1. Disables the I2C module.
  2. Enables the I2C module(1,2)
Note :
  1. Note: SDA and SCL pins must be configured for open-drain with internal or external pull-up
  2. SDA and SCL pins must be selected as both input and output in PPS
  3. CSTR can be set by more than one hardware source, all sources must be addressed by user software before the SCL line is released. CSTR is a module status bit, and does not show the true bus state.
  4. SMA is set on the same SCL edge as CSTR for a matching received address
  5. In this mode, ADRIE should be set, this allows an interrupt to clear the BCLIF condition and allow the ACK of matching address.
  6. In 10-bit Slave mode, when ADB = 1, CSTR will set when the high address has not been read out of I2CxRXB before the low address is shifted in. 

I2CxCON1

I2CxCON1: I2C CONTROL REGISTER 1

 CSD (R/W-0) (0.bit): Clock Stretching Disable bit (MODE<2:0> = 0xx & 11x)
  1. Slave clock stretching proceeds normally
  2. When SMA = 1, the CSTR bit will never be set
TXU (R/W/HC/HS-0) (1.bit): Transmit Underflow Status bit (MODE<2:0> = 0xx & 11x)
This bit can only be set when CSTRDIS = 1
  1. No slave underflow condition
  2. Set when SMA = 1, and a master clocks out data when TXBE = 1
RXO (R/W/HC/HS-0) (2.bit): Receive Overflow Status bit (MODE<2:0> = 0xx & 11x)This bit can only be set when CSD = 1
  1. No slave overflow condition
  2. Set when SMA = 1, and a master clocks in data when RXBF = 1
--- (3.bit): Reads as 1'b0
ACKT (R-0) (4.bit): Acknowledge Time Status bit
  1. Address holding and interrupt is disabled
  2. When ADRIF is set; CSTR is set
ACKSTAT (R-0) (5.bit): Nyugtázó állapotjelző bit. Csak adatküldéskor.
  1. Legutóbbio átvitelkor küldött nyugtázást a fogadó
  2. Nem küldött a fogadó nyugtázó jelet
ACKDT (R/W-0) (6.bit): Nyugtázó adatbit (1,2)
A megfelelő cím után továbbított érték nyugtázása
Acknowledge value transmitted after received data, when I2CCNT! = 0
  1. Pozitív nyugtázójelet küld az adatvonalra
  2. Negatív nyugtázójelet küld az adatvonalra  IDÁIG!!!
    NACK-ot küld a mester amikor az utolsó adatot nyugtázza
ACKCNT(R/W-0) (7.bit): Acknowledge End of Count bit(2)
Acknowledge value transmitted after received data, when I2CCNT = 0
Nyugtázó jelet küd vagy nem küld az adatfogadás után, ha I2CCNT=0
  1. Acknowledge (copied to SDA output)
  2. Not Acknowledge (copied to SDA output)
Note 1:Enabled interrupt flags are OR’d to produce the PIRx<I2CxIF> bit.














 
ACKTIE (R/W-0) (6.bit): Acknowledge Interrupt and Hold Enable bit.
Nyugtázáskor és a nyugtázási idő alatt a megszakítást engedélyező bit beállítása
  1. Nyugtázáskor és az erres zánt idő alatt nincs megszakítás
  2.  Ha ACKTIF=1 és még ha:
    ha  ACK jel megvalósult és a CSTR 1-et jelez.
    vagy ha  NACK jel megvalósult, CSTR bit nem változott
CNTIE (R/W-0) (7.bit): Byte Count Interrupt Enable bit
  1. CNTIE: Byte Count Interrupt Enable bit
  2. When CNTIF is set
Note :
  1. Software writes to ACKDT bit must be followed by a minimum SDA data-setup time before clearing CSTR.
  2. NACK may still be generated by I2C hardware when bus errors are indicated in the I2CxSTAT1 or I2CxERR registers.


 

I2CxCON1: I2C CONTROL REGISTER 1

 CSD (0.bit): Clock Stretching Disable bit (MODE<2:0> = 0xx & 11x)
  1. Slave clock stretching proceeds normally
  2. When SMA = 1, the CSTR bit will never be set
TXU (1.bit): Transmit Underflow Status bit (MODE<2:0> = 0xx & 11x)
This bit can only be set when CSTRDIS = 1
  1. No slave underflow condition
  2. Set when SMA = 1, and a master clocks out data when TXBE = 1
RXO (2.bit): Receive Overflow Status bit (MODE<2:0> = 0xx & 11x)This bit can only be set when CSD = 1
  1. No slave overflow condition
  2. Set when SMA = 1, and a master clocks in data when RXBF = 1
--- (3.bit): Reads as 1'b0
ACKT (4.bit): Acknowledge Time Status bit
  1. Address holding and interrupt is disabled
  2. When ADRIF is set; CSTR is set
ACKSTAT (5.bit): Acknowledge Status bit (Transmission only)
  1. Acknowledge was received for most recent transmission 
  2. Acknowledge was not received for most recent transmission
ACKDT (6.bit): Acknowledge Data bit(1,2)
Acknowledge value transmitted after matching address
Acknowledge value transmitted after received data, when I2CCNT! = 0
  1. Acknowledge (copied to SDA output)
  2.  Not Acknowledge (copied to SDA output)
ACKCNT (7.bit): Acknowledge End of Count bit(2)
Acknowledge value transmitted after received data, when I2CCNT = 0
  1. Acknowledge (copied to SDA output)
  2. Not Acknowledge (copied to SDA output)
Note 1:Enabled interrupt flags are OR’d to produce the PIRx<I2CxIF> bit.

 
ACKTIE (6.bit): Acknowledge Interrupt and Hold Enable bit
  1. Acknowledge holding and interrupt is disabled
  2.  When ACKTIF is set
    If ACK is generated, CSTR is also set.
    If NACK is generated, CSTR is unchanged
CNTIE (7.bit): Byte Count Interrupt Enable bit
  1. CNTIE: Byte Count Interrupt Enable bit
  2. When CNTIF is set
Note :
  1. Software writes to ACKDT bit must be followed by a minimum SDA data-setup time before clearing CSTR.
  2. NACK may still be generated by I2C hardware when bus errors are indicated in the I2CxSTAT1 or I2CxERR registers.

 

I2CxCON2
I2CxCON2: I2C CONTROL REGISTER 2

 BFRET <1:0> (R/W-0) (0-1bit): Bus Free Time Selection bits
 
BFRET<1:0> Bus Free Time Selection bits
11 64 I2C Clock pulses
10 32 I2C Clock pulses
01 16 I2C Clock pulses
00 8 I2C Clock pulses
 

 SDAHT<1:0> (R/W-0) (2-3bit): SDA Hold Time Selection bits
 
BFRET
<1:0>		 Bus Free Time Selection bits
11 Reserved
10 Minimum of 30 ns hold time on SDA after the falling edge of SCL
01 Minimum of 100 ns hold time on SDA after the falling edge of SCL
00 Minimum of 300 ns hold time on SDA after the falling edge of SCL
 
 
ADB (R/W-0) (4.bit): Address Data Buffer Disable bit
  1. Received address data is loaded only into the I2CADB Transmitted address data is loaded from the I2CADB0/1 registers.
  2. Received address data is loaded into both the I2CADB and I2CRXB Transmitted address data is loaded from the I2CTXB
FME (R/W-0) (5.bit): Fast Mode Enable bit
  1. SCL is sampled high twice before driving SCL low. (FSCL = FCLK/5)
  2. SCL is sampled high only once before driving SCL low. (FSCL = FCLK/4)
GCEN (R/W-0) (6.bit): General Call Address Enable bit (MODE<2:0> = 00x & 11x)
  1. General call address disabled
  2. General call address, 0x00, causes address match event
ACNT (R/W-0) (7.bit): Auto-Load I2C Count Register Enable bit
  1. Auto-load of I2CCNT disabled
  2.  The first received or transmitted byte after the address, is automatically loaded into the I2CCNT register. The I2CCNT register is loaded at the same time as the value is moved to/from the shifter. ACKDT is used to determine the ACK/NACK value for the address bytes and first data byte of a received message. This prevents a I2CCNT<NACK> from being sent for the byte that would update the I2CCNT register.


 
I2CxCON2: I2C CONTROL REGISTER 2

 BFRET<1:0> (0-1bit): Bus Free Time Selection bits
 
BFRET<1:0> Bus Free Time Selection bits
11 64 I2C Clock pulses
10 32 I2C Clock pulses
01 16 I2C Clock pulses
00 8 I2C Clock pulses
 

 SDAHT<1:0> (2-3bit): SDA Hold Time Selection bits
 
BFRET
<1:0>		 Bus Free Time Selection bits
11 Reserved
10 Minimum of 30 ns hold time on SDA after the falling edge of SCL
01 Minimum of 100 ns hold time on SDA after the falling edge of SCL
00 Minimum of 300 ns hold time on SDA after the falling edge of SCL
 
 
ADB (4.bit): Address Data Buffer Disable bit
  1. Received address data is loaded only into the I2CADB Transmitted address data is loaded from the I2CADB0/1 registers.
  2. Received address data is loaded into both the I2CADB and I2CRXB Transmitted address data is loaded from the I2CTXB
FME (5.bit): Fast Mode Enable bit
  1. SCL is sampled high twice before driving SCL low. (FSCL = FCLK/5)
  2. SCL is sampled high only once before driving SCL low. (FSCL = FCLK/4)
GCEN (6.bit): General Call Address Enable bit (MODE<2:0> = 00x & 11x)
  1. General call address disabled
  2. General call address, 0x00, causes address match event
ACNT (7.bit): Auto-Load I2C Count Register Enable bit
  1. Auto-load of I2CCNT disabled
  2.  The first received or transmitted byte after the address, is automatically loaded into the I2CCNT register. The I2CCNT register is loaded at the same time as the value is moved to/from the shifter. ACKDT is used to determine the ACK/NACK value for the address bytes and first data byte of a received message. This prevents a I2CCNT<NACK> from being sent for the byte that would update the I2CCNT register.

 

I2CxADR0		 ADR<7-0> (0-7bit): Address 1 bits
  • MODE<2:0> = 00x | 11x - 7-bit Slave/Multi-Master Modes
    DR0<7:1>:7-bit Slave Address
    ADR0<0>:Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x - 10-bit Slave Modes
    ADR0<7:0>: Eight Least Significant bits of 10-bit address 0 

 		 ADR<7-0> (0-7bit): Address 1 bits
  • MODE<2:0> = 00x | 11x - 7-bit Slave/Multi-Master Modes
    DR0<7:1>:7-bit Slave Address
    ADR0<0>:Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x - 10-bit Slave Modes
    ADR0<7:0>: Eight Least Significant bits of 10-bit address 0 

 

I2CxADR1
I2CxADR1: I2C ADDRESS 1 REGISTER

ADR<7-1> (1-7bit): Address or Divider bits

bit 0 Unimplemented: Read as ‘0’.
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>:7-bit Slave Address
    ADR<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master modes w/Masking
    MSK0<7:1>:7-bit Slave Address
    MSK0<0>:Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x - 10-bit Slave Modes
    ADR<14-10>:Bit pattern sent by master is fixed by I2C specification and must be equal to‘11110’. However, these bit values are compared by hardware to the received data to determine a match. It is up to the user to set these bits as ‘11110’.
    ADR<9-8>:Two Most Significant bits of 10-bit address
I2CxADR1: I2C ADDRESS 1 REGISTER

ADR<7-1> (1-7bit): Address or Divider bits

bit 0 Unimplemented: Read as ‘0’.
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>:7-bit Slave Address
    ADR<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master modes w/Masking
    MSK0<7:1>:7-bit Slave Address
    MSK0<0>:Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x - 10-bit Slave Modes
    ADR<14-10>:Bit pattern sent by master is fixed by I2C specification and must be equal to‘11110’. However, these bit values are compared by hardware to the received data to determine a match. It is up to the user to set these bits as ‘11110’.
    ADR<9-8>:Two Most Significant bits of 10-bit address

 

I2CxADR2
I2CxADR2: I2C ADDRESS 2 REGISTER

ADR<7-0>: Address 2 bits
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>:7-bit Slave Address

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master Modes with Masking
    ADR<7:1>:7-bit Slave Address

    MODE<2:0> = 010 - 10-Bit Slave Mode
    ADR<7:0>:Eight Least Significant bits  of second 10-bit address

    MODE<2:0> = 011 - 10-Bit Slave Mode with Masking
    MSK0<7-0>:The received address byte is masked, then compared to I2CxADR0
I2CxADR2: I2C ADDRESS 2 REGISTER

ADR<7-0>: Address 2 bits
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>:7-bit Slave Address

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master Modes with Masking
    ADR<7:1>:7-bit Slave Address

    MODE<2:0> = 010 - 10-Bit Slave Mode
    ADR<7:0>:Eight Least Significant bits  of second 10-bit address

    MODE<2:0> = 011 - 10-Bit Slave Mode with Masking
    MSK0<7-0>:The received address byte is masked, then compared to I2CxADR0


 

I2CxADR3
I2CXADR3: I2C ADDRESS 3 REGISTER
ADR<7-0> (0-7bit): Address 3 bits
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>:7-bit Slave Address
    ADR<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master Mode with Masking
    MSK1<7:1>:7-bit Slave Address
    MSK1<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 010 - 10-Bit Slave Mode
    ADR<14-10>: Bit pattern sent by master is fixed by I2C specification and must be equal to‘11110’. However, these bit values are compared by hardware to the received data to determine a match. It is up to the user to set these bits as ‘11110’
    ADR<9-8>: Two Most Significant bits of 10-bit address

    MODE<2:0> = 011 - 10-Bit Slave Mode with Masking
    MSK0<14-8>: The received address  byte, bit n, is  compared to I2CxADR0 to detect I2C address match

 
I2CXADR3: I2C ADDRESS 3 REGISTER
ADR<7-0> (0-7bit): Address 3 bits
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>:7-bit Slave Address
    ADR<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master Mode with Masking
    MSK1<7:1>:7-bit Slave Address
    MSK1<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 010 - 10-Bit Slave Mode
    ADR<14-10>: Bit pattern sent by master is fixed by I2C specification and must be equal to‘11110’. However, these bit values are compared by hardware to the received data to determine a match. It is up to the user to set these bits as ‘11110’
    ADR<9-8>: Two Most Significant bits of 10-bit address

    MODE<2:0> = 011 - 10-Bit Slave Mode with Masking
    MSK0<14-8>: The received address  byte, bit n, is  compared to I2CxADR0 to detect I2C address match


 

I2CxADB0
I2CxADB0: I2C ADDRESS DATA BUFFER 0 REGISTER (1)
bit 7-0
  • MODE<2:0> = 00x  
    ADB<7:1>: Address Data byte
    Received matching 7-bit slave address data
    R/!W: Read/not-Write Data bit  
    Received read/write value from 7-bit address byte

    MODE<2:0> = 01x
    ADB<7:0>: Address Data byte  
    Received matching lower 8-bits of 10-bit slave address data

    MODE<2:0> = 100
    Unused in this mode; bit state is a don’t care

    MODE<2:0> = 101
    ADB<7:0>: Low Address Data byte
    Low 10-bit address value copied to transmit shift register

    MODE<2:0> = 11x
    ADB<7:1>: Address Data byte
    Received matching 7-bit slave address
    R/!W: Read/not-Write Data bit
    Received read/write value received 7-bit slave address byte
     
Note  1: This register is read only except in master, 10-bit Address mode (MODE<2:0> = 101).



 
I2CxADB0: I2C ADDRESS DATA BUFFER 0 REGISTER(1)
bit 7-0
  • MODE<2:0> = 00x  
    ADB<7:1>: Address Data byte
    Received matching 7-bit slave address data
    R/!W: Read/not-Write Data bit  
    Received read/write value from 7-bit address byte

    MODE<2:0> = 01x
    ADB<7:0>: Address Data byte  
    Received matching lower 8-bits of 10-bit slave address data

    MODE<2:0> = 100
    Unused in this mode; bit state is a don’t care

    MODE<2:0> = 101
    ADB<7:0>: Low Address Data byte
    Low 10-bit address value copied to transmit shift register

    MODE<2:0> = 11x
    ADB<7:1>: Address Data byte
    Received matching 7-bit slave address
    R/!W: Read/not-Write Data bit
    Received read/write value received 7-bit slave address byte
     
Note  1: This register is read only except in master, 10-bit Address mode (MODE<2:0> = 101).

 

I2CxADB1
I2CxADB1: I2C ADDRESS DATA BUFFER 1 REGISTER(1)  
bit 7-0
  • MODE<2:0> = 00x
    Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x
    ADB<7:1>: 10-bit Address High byte
    Received matching 10-bit high address data
    R/!W: Read/not-Write Data bit
    Received read/write value from matching 10-bit high address

    MODE<2:0> = 100
    ADB<7:1>: Address Data byte
    7-bit address value copied to transmit shift register
    R/!W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations.

    MODE<2:0> = 101
    ADB<7:1>: 10-bit Address High Data byte
    10-bit high address value copied to transmit shift register
    R/!W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations.

    MODE<2:0> = 11x
    ADB<7:1>: Address Data byte
    7-bit address value copied to transmit shift register
    R/!W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations
 

Note 1:This register is read only in slave, 7-bit Addressing modes (MODE<2:0> = 0xx)


 
I2CxADB1: I2C ADDRESS DATA BUFFER 1 REGISTER(1)  
bit 7-0
  • MODE<2:0> = 00x
    Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x
    ADB<7:1>: 10-bit Address High byte
    Received matching 10-bit high address data
    R/!W: Read/not-Write Data bit
    Received read/write value from matching 10-bit high address

    MODE<2:0> = 100
    ADB<7:1>: Address Data byte
    7-bit address value copied to transmit shift register
    R/!W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations.

    MODE<2:0> = 101
    ADB<7:1>: 10-bit Address High Data byte
    10-bit high address value copied to transmit shift register
    R/!W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations.

    MODE<2:0> = 11x
    ADB<7:1>: Address Data byte
    7-bit address value copied to transmit shift register
    R/!W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations
 

Note 1:This register is read only in slave, 7-bit Addressing modes (MODE<2:0> = 0xx)

 

I2CxCNT
I2CxCNT: I2C BYTE COUNT REGISTER
bit 7-0 (0-7bit)
  • CNT<7:0>:I2C Byte Count Register bits
    If receiving data,
    decremented 8th SCL edge, when a new data byte is loaded into I2CxRXB

    If transmitting data,
    decremented 9th SCL edge, when a new data byte is moved from I2CxTXB
    CNTIF flag is set on 9th falling SCL edge, when I2CxCNT = 0. (Byte count cannot decrement past ‘0’)

    Note 1:It is recommended to write this register only when the module is IDLE (MMA = 0, SMA = 0) or when clock stretching (CSTR = 1 || MDR = 1).
Note 1:It is recommended to write this register only when the module is IDLE (MMA = 0, SMA = 0) or when clock stretching (CSTR = 1 || MDR = 1).

 
I2CxCNT: I2C BYTE COUNT REGISTER
bit 7-0 (0-7bit)
  • CNT<7:0>:I2C Byte Count Register bits
    If receiving data,
    decremented 8th SCL edge, when a new data byte is loaded into I2CxRXB

    If transmitting data,
    decremented 9th SCL edge, when a new data byte is moved from I2CxTXB
    CNTIF flag is set on 9th falling SCL edge, when I2CxCNT = 0. (Byte count cannot decrement past ‘0’)

    Note 1:It is recommended to write this register only when the module is IDLE (MMA = 0, SMA = 0) or when clock stretching (CSTR = 1 || MDR = 1).
Note 1:It is recommended to write this register only when the module is IDLE (MMA = 0, SMA = 0) or when clock stretching (CSTR = 1 || MDR = 1).

 

I2CxPIR
I2CxPIR: I2CxIF INTERRUPT FLAG REGISTER

SCIF (0.bit): Start Condition Interrupt Flag
  1. No Start condition detected
  2. Set on detection of Start condition
RSCIF (1.bit): Restart Condition Interrupt Flag
  1. No Restart condition detected
  2. Set on detection of Restart condition
PCIF (2.bit): Stop Condition Interrupt Flag
  1. No Stop condition detected
  2. Set on detection of Stop condition
ADRIF (3.bit): Address Interrupt Flag bit (MODE<2:0> = 0xx OR 11x)
  1. Address condition not detected
  2. Set the 8th falling edge of SCL for a matching received (high/low) address byte
ACKT (4.bit): Acknowledge Time Status bit
  1. Address holding and interrupt is disabled
  2. When ADRIF is set; CSTR is set
Unimplemented (5bit): Read as ‘0’
ACKTIF (6.bit): Acknowledge Status Time Interrupt Flag bit (2) (MODE<2:0> = 0xx OR 11x)
  1. Acknowledge condition not detected.
  2.  Set by the 9th falling edge of SCL for any byte when addressed as a Slave
CNTIF (7.bit): Byte Count Interrupt Flag bit
  1. I2CCNT condition has not occurred.
  2. When I2CCNT = 0, set by the 9th falling edge of SCL.
  1. Note: Enabled interrupt flags are OR’d to produce the PIRx<I2CxIF> bit.
  2. Note: ACKTIF is not set by a matching, 10-bit, high address byte with the R/W bit clear. It is only set after the matching low address byte is shifted in.


 
I2CxPIR: I2CxIF INTERRUPT FLAG REGISTER

SCIF (0.bit): Start Condition Interrupt Flag
  1. No Start condition detected
  2. Set on detection of Start condition
RSCIF (1.bit): Restart Condition Interrupt Flag
  1. No Restart condition detected
  2. Set on detection of Restart condition
PCIF (2.bit): Stop Condition Interrupt Flag
  1. No Stop condition detected
  2. Set on detection of Stop condition
ADRIF (3.bit): Address Interrupt Flag bit (MODE<2:0> = 0xx OR 11x)
  1. Address condition not detected
  2. Set the 8th falling edge of SCL for a matching received (high/low) address byte
ACKT (4.bit): Acknowledge Time Status bit
  1. Address holding and interrupt is disabled
  2. When ADRIF is set; CSTR is set
Unimplemented (5bit): Read as ‘0’
ACKTIF (6.bit): Acknowledge Status Time Interrupt Flag bit (2) (MODE<2:0> = 0xx OR 11x)
  1. Acknowledge condition not detected.
  2.  Set by the 9th falling edge of SCL for any byte when addressed as a Slave
CNTIF (7.bit): Byte Count Interrupt Flag bit
  1. I2CCNT condition has not occurred.
  2. When I2CCNT = 0, set by the 9th falling edge of SCL.
  1. Note: Enabled interrupt flags are OR’d to produce the PIRx<I2CxIF> bit.
  2. Note: ACKTIF is not set by a matching, 10-bit, high address byte with the R/W bit clear. It is only set after the matching low address byte is shifted in.

 

I2CxPIE

I2CxPIE: I2CxIE INTERRUPT AND HOLD ENABLE REGISTER

SCIE (0.bit): Start Condition Interrupt Enable
  1. Start detection interrupts are disabled
  2. Enable interrupt on detection of Start condition
RSCIE (1.bit): Restart Condition Interrupt Enable
  1. Start detection interrupts are disabled
  2. Enable interrupt on detection of Restart condition
PCIE (2.bit): Stop Condition Interrupt Enable
  1. Stop detection interrupts are disabled
  2. Enable interrupt on detection of Stop condition
ADRIE (3.bit): Address Interrupt and Hold Enable bit
  1. Address holding and interrupt is disabled
  2. When ADRIF is set; CSTR is set
WRIE (4.bit): Data Write Interrupt and Hold Enable bit
  1. Data Write holding and interrupt is disabled
  2. When WRIF is set; CSTR is set
Unimplemented (5bit): Read as ‘0’
ACKTIE (6.bit): Acknowledge Interrupt and Hold Enable bit
  1. Acknowledge holding and interrupt is disabled
  2. When ACKTIF is set
    If ACK is generated, CSTR is also set.
    If NACK is generated, CSTR is unchanged
CNTIE (7.bit): Byte Count Interrupt Enable bit
  1. Byte count interrupts are disabled
  2. When CNTIF is set.
  1. Note: Enabled interrupt flags are OR’d to produce the PIRx<I2CxIF> bit.

 

I2CxPIE: I2CxIE INTERRUPT AND HOLD ENABLE REGISTER

SCIE (0.bit): Start Condition Interrupt Enable
  1. Start detection interrupts are disabled
  2. Enable interrupt on detection of Start condition
RSCIE (1.bit): Restart Condition Interrupt Enable
  1. Start detection interrupts are disabled
  2. Enable interrupt on detection of Restart condition
PCIE (2.bit): Stop Condition Interrupt Enable
  1. Stop detection interrupts are disabled
  2. Enable interrupt on detection of Stop condition
ADRIE (3.bit): Address Interrupt and Hold Enable bit
  1. Address holding and interrupt is disabled
  2. When ADRIF is set; CSTR is set
WRIE (4.bit): Data Write Interrupt and Hold Enable bit
  1. Data Write holding and interrupt is disabled
  2. When WRIF is set; CSTR is set
Unimplemented (5bit): Read as ‘0’
ACKTIE (6.bit): Acknowledge Interrupt and Hold Enable bit
  1. Acknowledge holding and interrupt is disabled
  2. When ACKTIF is set
    If ACK is generated, CSTR is also set.
    If NACK is generated, CSTR is unchanged
CNTIE (7.bit): Byte Count Interrupt Enable bit
  1. Byte count interrupts are disabled
  2. When CNTIF is set.
  1. Note: Enabled interrupt flags are OR’d to produce the PIRx<I2CxIF> bit.



 

I2CxADR0
 I2CxADR0: I2C ADDRESS 0 REGISTER
bit 7-0:  ADR<7-0>: Address 1 bits
  • MODE<2:0> = 00x | 11x - 7-bit Slave/Multi-Master Modes
    ADR0<7:1>: 7-bit Slave Address
    ADR0<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x - 10-bit Slave Modes
    ADR0<7:0>: Eight Least Significant bits of 10-bit address 0 


 		  I2CxADR0: I2C ADDRESS 0 REGISTER
bit 7-0:  ADR<7-0>: Address 1 bits
  • MODE<2:0> = 00x | 11x - 7-bit Slave/Multi-Master Modes
    ADR0<7:1>: 7-bit Slave Address
    ADR0<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x - 10-bit Slave Modes
    ADR0<7:0>: Eight Least Significant bits of 10-bit address 0 

I2CxADR1		 I2CxADR1: I2C ADDRESS 1 REGISTER
bit 7-1: ADR[7-1]: Address or Divider bits
  • 0.bit = Unimplemented: Read as ‘0’.
     
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>: 7-bit Slave Address
    ADR<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master modes w/Masking
    MSK0<7:1>: 7-bit Slave Address
    MSK0<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x - 10-bit Slave Modes
    ADR<14-10>: Bit pattern sent by master is fixed by I2C specification and must be equal to‘11110’. However, these bit values are compared by hardware to the received data to determine a match. It is up to the user to set these bits as ‘11110’.
    ADR<9-8>: Two Most Significant bits of 10-bit address 

 		  I2CxADR1: I2C ADDRESS 1 REGISTER
bit 7-1: ADR[7-1]: Address or Divider bits
  • 0.bit = Unimplemented: Read as ‘0’.
     
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>: 7-bit Slave Address
    ADR<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master modes w/Masking
    MSK0<7:1>: 7-bit Slave Address
    MSK0<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x - 10-bit Slave Modes
    ADR<14-10>: Bit pattern sent by master is fixed by I2C specification and must be equal to‘11110’. However, these bit values are compared by hardware to the received data to determine a match. It is up to the user to set these bits as ‘11110’.
    ADR<9-8>: Two Most Significant bits of 10-bit address 



 

I2CxADR2
 I2CxADR2: I2C ADDRESS 2 REGISTER
bit 7-0:  ADR<7-0>: Address 2 bits
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>: 7-bit Slave Address

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master Modes with Masking
    ADR<7:1>: 7-bit Slave Address

    MODE<2:0> = 010 - 10-Bit Slave Mode
    ADR<7:0>: Eight Least Significant bits of second 10-bit address

    MODE<2:0> = 011 - 10-Bit Slave Mode with Masking
    MSK0<7-0>: The received address byte is masked, then compared to I2CxADR0


 
 I2CxADR2: I2C ADDRESS 2 REGISTER
bit 7-0:  ADR<7-0>: Address 2 bits
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>: 7-bit Slave Address

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master Modes with Masking
    ADR<7:1>: 7-bit Slave Address

    MODE<2:0> = 010 - 10-Bit Slave Mode
    ADR<7:0>: Eight Least Significant bits of second 10-bit address

    MODE<2:0> = 011 - 10-Bit Slave Mode with Masking
    MSK0<7-0>: The received address byte is masked, then compared to I2CxADR0

 

I2CxADR3
I2CxADR3: I2C ADDRESS 3 REGISTER
bit 7-0 ADR<7-0>: Address 3 bits
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>: 7-bit Slave Address
    ADR<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master Mode with Masking
    MSK1<7:1>: 7-bit Slave Address
    MSK1<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 010 - 10-Bit Slave Mode
    ADR<14-10>: Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, these bit values are compared by hardware to the received data to determine a match. It is up to the user to set these bits as ‘11110’
    ADR<9-8>: Two Most Significant bits of 10-bit address

    MODE<2:0> = 011 - 10-Bit Slave Mode with Masking
    MSK0<14-8>: The  received  address  byte,  bit  n, is compared to I2CxADR0 to detect I2C address match


 
 I2CxADR3: I2C ADDRESS 3 REGISTER
bit 7-0 ADR<7-0>: Address 3 bits
  • MODE<2:0> = 000 | 110 - 7-bit Slave/Multi-Master Modes
    ADR<7:1>: 7-bit Slave Address
    ADR<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 001 | 111 - 7-bit Slave/Multi-Master Mode with Masking
    MSK1<7:1>: 7-bit Slave Address
    MSK1<0>: Unused in this mode; bit state is a don’t care

    MODE<2:0> = 010 - 10-Bit Slave Mode
    ADR<14-10>: Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, these bit values are compared by hardware to the received data to determine a match. It is up to the user to set these bits as ‘11110’
    ADR<9-8>: Two Most Significant bits of 10-bit address

    MODE<2:0> = 011 - 10-Bit Slave Mode with Masking
    MSK0<14-8>: The  received  address  byte,  bit  n, is compared to I2CxADR0 to detect I2C address match

 

I2CxADB0		  I2CxADB0: I2C ADDRESS DATA BUFFER 0 REGISTER(1)
bit 7-0 
  • MODE<2:0> = 00x
    ADB<7:1>: Address Data byte
    Received matching 7-bit slave address data
    R/!W: Read/not-Write Data bit
    Received read/write value from 7-bit address byte

    MODE<2:0> = 01x
    ADB<7:0>: Address Data byte
    Received matching lower 8-bits of 10-bit slave address data
    MODE<2:0> = 100
    Unused in this mode; bit state is a don’t care

    MODE<2:0> = 101
    ADB<7:0>: Low Address Data byte
    Low 10-bit address value copied to transmit shift register

    MODE<2:0> = 11x
    ADB<7:1>: Address Data byte
    Received matching 7-bit slave address
    R/!W: Read/not-Write Data bit
    Received read/write value received 7-bit slave address byte
 
Note  1:This register is read only except in master, 10-bit Address mode (MODE<2:0> = 101).

 		  I2CxADB0: I2C ADDRESS DATA BUFFER 0 REGISTER(1)
bit 7-0 
  • MODE<2:0> = 00x
    ADB<7:1>: Address Data byte
    Received matching 7-bit slave address data
    R/!W: Read/not-Write Data bit
    Received read/write value from 7-bit address byte

    MODE<2:0> = 01x
    ADB<7:0>: Address Data byte
    Received matching lower 8-bits of 10-bit slave address data
    MODE<2:0> = 100
    Unused in this mode; bit state is a don’t care

    MODE<2:0> = 101
    ADB<7:0>: Low Address Data byte
    Low 10-bit address value copied to transmit shift register

    MODE<2:0> = 11x
    ADB<7:1>: Address Data byte
    Received matching 7-bit slave address
    R/!W: Read/not-Write Data bit
    Received read/write value received 7-bit slave address byte
 
Note  1:This register is read only except in master, 10-bit Address mode (MODE<2:0> = 101).

 

I2CxADB1
 I2CxADB1: I2C ADDRESS DATA BUFFER 1 REGISTER(1)
bit 7-0 
  •  MODE<2:0> = 00x
    Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x
    ADB<7:1>: 10-bit Address High byte
    Received matching 10-bit high address data
    R/!W: Read/not-Write Data bit
    Received read/write value from matching 10-bit high address

    MODE<2:0> = 100
    ADB<7:1>: Address Data byte
    7-bit address value copied to transmit shift register
    R/W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations.

    MODE<2:0> = 101
    ADB<7:1>: 10-bit Address High Data byte
    10-bit high address value copied to transmit shift register
    R/!W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations.

    MODE<2:0> = 11x
    ADB<7:1>: Address Data byte
    7-bit address value copied to transmit shift register
    R/!W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations
Note 1: This register is read only in slave, 7-bit Addressing modes (MODE<2:0> = 0xx)


 
 I2CxADB1: I2C ADDRESS DATA BUFFER 1 REGISTER(1)
bit 7-0 
  •  MODE<2:0> = 00x
    Unused in this mode; bit state is a don’t care

    MODE<2:0> = 01x
    ADB<7:1>: 10-bit Address High byte
    Received matching 10-bit high address data
    R/!W: Read/not-Write Data bit
    Received read/write value from matching 10-bit high address

    MODE<2:0> = 100
    ADB<7:1>: Address Data byte
    7-bit address value copied to transmit shift register
    R/W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations.

    MODE<2:0> = 101
    ADB<7:1>: 10-bit Address High Data byte
    10-bit high address value copied to transmit shift register
    R/!W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations.

    MODE<2:0> = 11x
    ADB<7:1>: Address Data byte
    7-bit address value copied to transmit shift register
    R/!W: Read/not-Write Data bit
    Read/write value copied to transmit shift register
    Master hardware uses this bit to produce read versus write operations
Note 1: This register is read only in slave, 7-bit Addressing modes (MODE<2:0> = 0xx)
 
     
     
     
     
     
     

 

 

 

         
BTO<2:0>
I2CxBTO		 BTO: / I2C BUS TIMEOUT SELECTION REGISTER/