Pic18FxxK42 konfigurálás

Beküldte root - k, 01/23/2018 - 21:45

Adatlap (pdf): PIC18F(L)xxK42.pdf

MAGYAR

;
;   IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
;              superseded by the CONFIG directive.  The following settings
;              are available for this device.
;
;   External Oscillator Selection:
  Kulso oszcillator vagy orajelvalasztas (Kat.: 66. old. Modulrajz: 93. old.)
;  CONFIG  FEXTOSC = LP ;        LP (crystal oscillator) optimized for 32.768 kHz; PFM set to low power
                                             ; Alacsony frekvenciaju (32.768 kHz-re optimalizalt) kristaly oszcillator hasznalata
;  CONFIG  FEXTOSC = XT ;        XT (crystal oscillator) above 100 kHz, below 8 MHz; PFM set to medium power
                                              ; Kozepes frekvenciaju (100kHz és 8 MHz kozott) kristaly oszcillator hasznalata
;  CONFIG  FEXTOSC = HS ;        HS (crystal oscillator) above 8 MHz; PFM set to high power
                                              ;  Magas frekvenciaju (8 MHz felett) kristaly oszcillator hasznalata
;  CONFIG  FEXTOSC = RESERVED ; Reserved (DO NOT USE) - Fenntartva (NE HASZNÁLD)
;  CONFIG  FEXTOSC = OFF ;       Oscillator not enabled - Oszcillator nincs engedelyezve
;  CONFIG  FEXTOSC = ECL ;       EC (external clock) below 100 kHz; PFM set to low power
                                                ; EC (external clock) vagyis kulso orajel 100 Khz alatt. Ilyenkor az egyik oszcillatollab felszabadul me celra.
;  CONFIG  FEXTOSC = ECM ;       EC (external clock) for 500 kHz to 8 MHz; PFM set to medium power
                                                 ; EC (external clock) vagyis kulso orajel 500 Khz es 8 MHz kozott. Ilyenkor az egyik oszcillatollab felszabadul me celra.
;  CONFIG  FEXTOSC = ECH ;       EC (external clock) above 8 MHz; PFM set to high power
                                                 ; EC (external clock) vagyis kulso orajel 8 Mhz felett. Ilyenkor az egyik oszcillatollab felszabadul me celra.
                                                 ; 
;
;   Reset Oscillator Selection:
; Indulaskor mas orajelforras is lehet, amit itt lehet beallitani:
;  CONFIG  RSTOSC = HFINTOSC_64MHZHFINTOSC ;  with HFFRQ = 64 MHz and CDIV = 1:1
                                                                                          ; Magas frekvenciaju belso oszcillator magas ferkvencias beallitassal
;  CONFIG  RSTOSC = RESERVED_1 ; Reserved - Fenntartott. Ne haszmáljuk!
;  CONFIG  RSTOSC = EXTOSC_4PLL EXTOSC ; with 4x PLL, with EXTOSC operating per FEXTOSC bits
;  CONFIG  RSTOSC = RESERVED_2 ; Reserved  - Fenntartott. Ne haszmáljuk!
;  CONFIG  RSTOSC = SOSC ;       Secondary Oscillator - Masodlagos oszcillator (Timer0)
;  CONFIG  RSTOSC = LFINTOSC ;   Low-Frequency Oscillator - Alacsony frekvenciaju belso oszcillator, ami 31 Khz-es belso oszcillator
;  CONFIG  RSTOSC = HFINTOSC_1MHZHFINTOSC ; with HFFRQ = 4 MHz and CDIV = 4:1 - Magas frekvenciaju belso oszcillator
                                                                                       ;    ??????  kozepes frekvencias beallitassal                                                                                 ;
;  CONFIG  RSTOSC = EXTOSC ;     EXTOSC operating per FEXTOSC bits (device manufacturing default)
                                                      ; Kulso oszcillatoros mukodes a fentebb beallitott FEXTOSC szerint. Nincs ketsebesseges indulas.
                                                      ;Ez az alapertelmezett beallitas.
;
;   Clock out Enable bit:
;  CONFIG  CLKOUTEN = ON ;       CLKOUT function is enabled
;  CONFIG  CLKOUTEN = OFF ;      CLKOUT function is disabled
;
;   PRLOCKED One-Way Set Enable bit:
;  CONFIG  PR1WAY = OFF ;        PRLOCK bit can be set and cleared repeatedly
;  CONFIG  PR1WAY = ON ;         PRLOCK bit can be cleared and set only once
;
;   Clock Switch Enable bit:
;  CONFIG  CSWEN = OFF ;         The NOSC and NDIV bits cannot be changed by user software
;  CONFIG  CSWEN = ON ;          Writing to NOSC and NDIV is allowed
;
;   Fail-Safe Clock Monitor Enable bit:
; CPU orajelforras figyelesenek engedelyezese/tiltasa. Pld. ha a kulso oszcillator meghibasodik, azt tudja ezaltal erzekelni.
; Referenciaforrasnak az erzekelesre a 31 KHz-es TFINTOSC-ot hasznalja. Hiany eseten lehetoseg van beavatkozasra. 
;  CONFIG  FCMEN = OFF ;         Fail-Safe Clock Monitor disabled - Tiltja a CPU orajel figyelest
;  CONFIG  FCMEN = ON  ;         Fail-Safe Clock Monitor enabled - Engedelyezi a CPU orajel figyelest

;   MCLR Enable bit: ???? at kell majd irni
; MCLR, vagyis a kulso reset lab beallitasa resetnek vagy digitalis I/O-nak
;  CONFIG  MCLRE = INTMCLR ;     If LVP = 0, MCLR pin function is port defined function; If LVP =1, RE3 pin fuction is MCLR
; Ha LVP=0, akkor port labkent funkcional programozo csatlakoztatasahoz. Ha LVP=1, akkor digitalis I/O lesz RE3 neven.
;  CONFIG  MCLRE = EXTMCLR ;     If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR 
; Ha LVP=0, akkor RESET labkent funkcional
;
;   Power-up timer selection bits:
; Tapfeszultseg felallasakor a kesleltetesi ido kivalasztasa. Ez fokent a kvarc beallasanak kell, ha kell.
;  CONFIG  PWRTS = PWRT_1 ;      PWRT set at 1ms
;  CONFIG  PWRTS = PWRT_16 ;     PWRT set at 16ms
;  CONFIG  PWRTS = PWRT_64 ;     PWRT set at 64ms
;  CONFIG  PWRTS = PWRT_OFF ;    PWRT is disabled
;
;   Multi-vector enable bit:
;   CONFIG  MVECEN = OFF ;        Interrupt contoller does not use vector table to prioritze interrupts
;   CONFIG  MVECEN = ON ;         Multi-vector enabled, Vector table used for interrupts
;
;   IVTLOCK bit One-way set enable bit:
;  CONFIG  IVT1WAY = OFF ;       IVTLOCK bit can be cleared and set repeatedly
;  CONFIG  IVT1WAY = ON ;       IVTLOCK bit can be cleared and set only once
;
;   Low Power BOR Enable bit:
;  CONFIG  LPBOREN = ON ;        ULPBOR enabled
;  CONFIG  LPBOREN = OFF ;       ULPBOR disabled
;
;   Brown-out Reset Enable bits:
; Tapfeszultseg csokkenes altal kivaltott RESET feltetelek beallitasa
;  CONFIG  BOREN = OFF ;         Brown-out Reset disabled - Tapfeszulseg csokkenes eseten nincs RESET
;  CONFIG  BOREN = ON ;          Brown-out Reset enabled according to SBOREN
                                          ; Tapfeszültseg csokkenes eseten a RESET-et a SBOREN hatarozza meg, vagyis engedelyezheti
;  CONFIG  BOREN = NOSLP ;       Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored - Tapfeszültseg csokkenes eseten a
                                                 ;  Reset futás közben engedelyezve, alvó üzemmódban le van tiltva. A SBOREN-t figyelmen kívül hagyja.
;  CONFIG  BOREN = SBORDIS ;     Brown-out Reset enabled , SBOREN bit is ignored - Tapfeszültseg csokkenes eseten mindenkeppen
                                                     ; RESET tortenik az engedelyezestol fuggetlenul. A SBOREN-t figyelmen kívül hagyja.
;
;   Brown-out Reset Voltage Selection bits:
; Tapfeszultseg eseskor a RESET beallasanak erteke valaszthato meg
;  CONFIG  BORV = VBOR_2P85 ;    Brown-out Reset Voltage (VBOR) set to 2.8V
;  CONFIG  BORV = VBOR_2P7 ;     Brown-out Reset Voltage (VBOR) set to 2.7V
;  CONFIG  BORV = VBOR_245 ;     Brown-out Reset Voltage (VBOR) set to 2.45V
;  CONFIG  BORV = VBOR_190 ;     Brown-out Reset Voltage (VBOR) set to 1.90V
;
;   ZCD Disable bit:
;  CONFIG ZCD = ON ;            ZCD always enabled
;  CONFIG ZCD = OFF ;           ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
;
;   PPSLOCK bit One-Way Set Enable bit:
; A modulok ill. periferiak labhoz kapcsolasanak csak egyszeri, vagy tobbszori engedelyezese.
; Megj.: Programban csak adddig oldjuk fel egy spesialis szekvenciaval,  mig tart az osszerendeles, utana a specialais szekvenciaval LOCK-olni kell! 
;  CONFIG  PPS1WAY = OFF ;       PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
                                                ; Tobbszor is hozzarendelhetjuk a labakhoz a portokat (modulokat).
;  CONFIG  PPS1WAY = ON  ;       PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
                                                ; Csak egyszer rendelhetjuk hozza a labakhoz a portokat (modulokat).
;
;   Stack Full/Underflow Reset Enable bit:
; Verem tulcsordulas, alulcsordulas eseten a RESET engedelyezese vagy tiltasa
;  CONFIG  STVREN = OFF ;        Stack full/underflow will not cause Reset - Tiltva a RESET
;  CONFIG  STVREN = ON ;         Stack full/underflow will cause Reset - Engedelyezve a RESET
;
;   Debugger Enable bit:
;  CONFIG   DEBUG = ON ;          Background debugger enabled - Debug engedelyezett
;  CONFIG  DEBUG = OFF ;         Background debugger disabled - Debug tiltott (ezt szoktam hasznalni)
;
;   Extended Instruction Set Enable bit:
; Kiterjesztett utasitasok hasznalatanak beallitasa. C programozasnak hasznalatos a kiterjesztes.
;  CONFIG  XINST = ON ;          Extended Instruction Set and Indexed Addressing Mode enabled - Engedelyzett
;  CONFIG  XINST = OFF ;         Extended Instruction Set and Indexed Addressing Mode disabled - Tiltott
;
;   WDT Period selection bits:
; WDT szamlalonak a frekvencialeosztas kivalasztasa. Az idoertekek 31 KHz bemeneti frekvenciara vannak megadva!
; Programbol nem figyelheto a szamlalo, kivetel a  WDTCPS_31 beallitasnal a WDTPS-el.
;  CONFIG  WDTCPS = WDTCPS_0 ;   Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_1 ;   Divider ratio 1:64 -> 31 KHz= 2ms
;  CONFIG  WDTCPS = WDTCPS_2 ;   Divider ratio 1:128 -> 31 KHz= 4ms
;  CONFIG  WDTCPS = WDTCPS_3 ;   Divider ratio 1:256 -> 31 KHz= 8ms
;  CONFIG  WDTCPS = WDTCPS_4 ;   Divider ratio 1:512 -> 31 KHz= 16ms
;  CONFIG  WDTCPS = WDTCPS_5 ;   Divider ratio 1:1024 -> 31 KHz= 32ms
;  CONFIG  WDTCPS = WDTCPS_6 ;   Divider ratio 1:2048 -> 31 KHz= 64ms
;  CONFIG  WDTCPS = WDTCPS_7 ;   Divider ratio 1:4096 -> 31 KHz= 128ms
;  CONFIG  WDTCPS = WDTCPS_8 ;   Divider ratio 1:8192 -> 31 KHz= 256ms
;  CONFIG  WDTCPS = WDTCPS_9 ;   Divider ratio 1:16384 -> 31 KHz= 512ms
;  CONFIG  WDTCPS = WDTCPS_10 ;  Divider ratio 1:32768 -> 31 KHz= 1s
;  CONFIG  WDTCPS = WDTCPS_11 ;  Divider ratio 1:65536 -> 31 KHz= 2s
;  CONFIG  WDTCPS = WDTCPS_12 ;  Divider ratio 1:131072 -> 31 KHz= 4s
;  CONFIG  WDTCPS = WDTCPS_13 ;  Divider ratio 1:262144 -> 31 KHz= 8s
;  CONFIG  WDTCPS = WDTCPS_14 ;  Divider ratio 1:524299 -> 31 KHz= 16s
;  CONFIG  WDTCPS = WDTCPS_15 ;  Divider ratio 1:1048576 -> 31 KHz= 32s
;  CONFIG  WDTCPS = WDTCPS_16 ;  Divider ratio 1:2097152 -> 31 KHz= 64s
;  CONFIG  WDTCPS = WDTCPS_17 ;  Divider ratio 1:4194304 -> 31 KHz= 128s
;  CONFIG  WDTCPS = WDTCPS_18 ;  Divider ratio 1:8388608 -> 31 KHz= 256s
;  CONFIG  WDTCPS = WDTCPS_19 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_20 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_21 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_22 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_23 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_24 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_25 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_26 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_27 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_28 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_29 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_30 ;  Divider ratio 1:32 -> 31 KHz= 1ms
;  CONFIG  WDTCPS = WDTCPS_31 ;  Divider ratio 1:65536; programbol figyelheto WDTPS -> 31 KHz= 2s
;
;   WDT operating mode:
; WDT lefagyasfigyelo uzemmodjanak megvalasztasa
;     WDTE = OFF           WDT Disabled; SWDTEN is ignored - Nincs engedelyezve fuggetlenul az SWDTEN-tol
;     WDTE = SWDTEN        WDT enabled/disabled by SWDTEN bit - Engedelyezest az SWDTEN bit hatarozza meg
;     WDTE = NSLEEP        WDT enabled while sleep=0, suspended when sleep=1; SWDTEN ignored
                                      ; WDT engedelyezve ha sleep=0, felfuggeszt ha sleep=1. SWDTEN hatastalan.
;     WDTE = ON            WDT enabled regardless of sleep - Engedelyezett, fuggetlenul az alvo uzemmodzol.
;
;   WDT Window Select bits:
;  CONFIG  WDTCWS = WDTCWS_0 ;   window delay = 87.5; no software control; keyed access required
;  CONFIG  WDTCWS = WDTCWS_1 ;   window delay = 75 percent of time; no software control; keyed access required
;  CONFIG  WDTCWS = WDTCWS_2 ;   window delay = 62.5 percent of time; no software control; keyed access required
;  CONFIG  WDTCWS = WDTCWS_3 ;   window delay = 50 percent of time; no software control; keyed access required
;  CONFIG  WDTCWS = WDTCWS_4 ;   window delay = 37.5 percent of time; no software control; keyed access required
;  CONFIG  WDTCWS = WDTCWS_5 ;   window delay = 25 percent of time; no software control; keyed access required
;  CONFIG  WDTCWS = WDTCWS_6 ;   window always open (100%); no software control; keyed access required
;  CONFIG  WDTCWS = WDTCWS_7 ;   window always open (100%); software control; keyed access not required
;
;   WDT input clock selector:
; WDT lefagyasfigyelo szamlalojanak orajelforras kivalasztas Lasd: Kat.: 93. old.
;  CONFIG  WDTCCS = LFINTOSC ;   WDT reference clock is the 31.0 kHz LFINTOSC
;  CONFIG  WDTCCS = MFINTOSC ;   WDT reference clock is the 32kHz MFINTOSC output
;  CONFIG  WDTCCS = SOSC ;       WDT reference clock is SOSC - Masodlagos kulso (Tim0) oszcillator
;  CONFIG  WDTCCS = SC ;         Software Control - ????????????
;
;   Boot Block Size selection bits:
;  CONFIG  BBSIZE = BBSIZE_8192 ; Boot Block size is 8192 words
;  CONFIG  BBSIZE = BBSIZE_4096 ; Boot Block size is 4096 words
;  CONFIG  BBSIZE = BBSIZE_2048 ; Boot Block size is 2048 words
;  CONFIG  BBSIZE = BBSIZE_1024 ; Boot Block size is 1024 words
;  CONFIG  BBSIZE = BBSIZE_512 ;   Boot Block size is 512 words
;
;   Boot Block enable bit:
;  CONFIG  BBEN = ON ;           Boot block enabled
;  CONFIG  BBEN = OFF ;          Boot block disabled
;
;   Storage Area Flash enable bit:
;  CONFIG  SAFEN = ON ;          SAF enabled
;  CONFIG  SAFEN = OFF ;         SAF disabled
;
;   Application Block write protection bit:
;  CONFIG  WRTAPP = ON ;         Application Block write protected
;  CONFIG  WRTAPP = OFF ;        Application Block not write protected
;
;   Configuration Register Write Protection bit:
;  CONFIG  WRTB = ON ;           Configuration registers (300000-30000Bh) write-protected
;  CONFIG  WRTB = OFF ;          Configuration registers (300000-30000Bh) not write-protected
;
;   Boot Block Write Protection bit:
;  CONFIG  WRTC = ON ;           Boot Block (000000-0007FFh) write-protected
;  CONFIG  WRTC = OFF ;          Boot Block (000000-0007FFh) not write-protected
;
;   Data EEPROM Write Protection bit:
;  CONFIG  WRTD = ON ;           Data EEPROM write-protected
;  CONFIG  WRTD = OFF ;          Data EEPROM not write-protected
;
;   SAF Write protection bit:
;  CONFIG  WRTSAF = ON ;         SAF Write Protected
;  CONFIG WRTSAF = OFF ;        SAF not Write Protected
;
;   Low Voltage Programming Enable bit:
;  CONFIG  LVP = OFF ;           HV on MCLR/VPP must be used for programming
;  CONFIG  LVP = ON ;            Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored
;
;   PFM and Data EEPROM Code Protection bit:
;  CONFIG  CP = ON ;             PFM and Data EEPROM code protection enabled
;  CONFIG  CP = OFF ;           PFM and Data EEPROM code protection disabled
;

;

ANGOL;


;   IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
;              superseded by the CONFIG directive.  The following settings
;              are available for this device.
;
;   External Oscillator Selection:
;     FEXTOSC = LP         LP (crystal oscillator) optimized for 32.768 kHz; PFM set to low power
;     FEXTOSC = XT         XT (crystal oscillator) above 100 kHz, below 8 MHz; PFM set to medium power
;     FEXTOSC = HS         HS (crystal oscillator) above 8 MHz; PFM set to high power
;     FEXTOSC = RESERVED   Reserved (DO NOT USE)
;     FEXTOSC = OFF        Oscillator not enabled
;     FEXTOSC = ECL        EC (external clock) below 100 kHz; PFM set to low power
;     FEXTOSC = ECM        EC (external clock) for 500 kHz to 8 MHz; PFM set to medium power
;     FEXTOSC = ECH        EC (external clock) above 8 MHz; PFM set to high power
;
;   Reset Oscillator Selection:
;     RSTOSC = HFINTOSC_64MHZHFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1
;     RSTOSC = RESERVED_1  Reserved
;     RSTOSC = EXTOSC_4PLL EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
;     RSTOSC = RESERVED_2  Reserved
;     RSTOSC = SOSC        Secondary Oscillator
;     RSTOSC = LFINTOSC    Low-Frequency Oscillator
;     RSTOSC = HFINTOSC_1MHZHFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1
;     RSTOSC = EXTOSC      EXTOSC operating per FEXTOSC bits (device manufacturing default)
;
;   Clock out Enable bit:
;     CLKOUTEN = ON        CLKOUT function is enabled
;     CLKOUTEN = OFF       CLKOUT function is disabled
;
;   PRLOCKED One-Way Set Enable bit:
;     PR1WAY = OFF         PRLOCK bit can be set and cleared repeatedly
;     PR1WAY = ON          PRLOCK bit can be cleared and set only once
;
;   Clock Switch Enable bit:
;     CSWEN = OFF          The NOSC and NDIV bits cannot be changed by user software
;     CSWEN = ON           Writing to NOSC and NDIV is allowed
;
;   Fail-Safe Clock Monitor Enable bit:
;     FCMEN = OFF          Fail-Safe Clock Monitor disabled
;     FCMEN = ON           Fail-Safe Clock Monitor enabled
;
;   MCLR Enable bit:
;     MCLRE = INTMCLR      If LVP = 0, MCLR pin function is port defined function; If LVP =1, RE3 pin fuction is MCLR
;     MCLRE = EXTMCLR      If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR 
;
;   Power-up timer selection bits:
;     PWRTS = PWRT_1       PWRT set at 1ms
;     PWRTS = PWRT_16      PWRT set at 16ms
;     PWRTS = PWRT_64      PWRT set at 64ms
;     PWRTS = PWRT_OFF     PWRT is disabled
;
;   Multi-vector enable bit:
;     MVECEN = OFF         Interrupt contoller does not use vector table to prioritze interrupts
;     MVECEN = ON          Multi-vector enabled, Vector table used for interrupts
;
;   IVTLOCK bit One-way set enable bit:
;     IVT1WAY = OFF        IVTLOCK bit can be cleared and set repeatedly
;     IVT1WAY = ON         IVTLOCK bit can be cleared and set only once
;
;   Low Power BOR Enable bit:
;     LPBOREN = ON         ULPBOR enabled
;     LPBOREN = OFF        ULPBOR disabled
;
;   Brown-out Reset Enable bits:
;     BOREN = OFF          Brown-out Reset disabled
;     BOREN = ON           Brown-out Reset enabled according to SBOREN
;     BOREN = NOSLP        Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored
;     BOREN = SBORDIS      Brown-out Reset enabled , SBOREN bit is ignored
;
;   Brown-out Reset Voltage Selection bits:
;     BORV = VBOR_2P85     Brown-out Reset Voltage (VBOR) set to 2.8V
;     BORV = VBOR_2P7      Brown-out Reset Voltage (VBOR) set to 2.7V
;     BORV = VBOR_245      Brown-out Reset Voltage (VBOR) set to 2.45V
;     BORV = VBOR_190      Brown-out Reset Voltage (VBOR) set to 1.90V
;
;   ZCD Disable bit:
;     ZCD = ON             ZCD always enabled
;     ZCD = OFF            ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
;
;   PPSLOCK bit One-Way Set Enable bit:
;     PPS1WAY = OFF        PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
;     PPS1WAY = ON         PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
;
;   Stack Full/Underflow Reset Enable bit:
;     STVREN = OFF         Stack full/underflow will not cause Reset
;     STVREN = ON          Stack full/underflow will cause Reset
;
;   Debugger Enable bit:
;     DEBUG = ON           Background debugger enabled
;     DEBUG = OFF          Background debugger disabled
;
;   Extended Instruction Set Enable bit: 
;     XINST = ON           Extended Instruction Set and Indexed Addressing Mode enabled 
;     XINST = OFF          Extended Instruction Set and Indexed Addressing Mode disabled 
;
;   WDT Period selection bits:
;     WDTCPS = WDTCPS_0    Divider ratio 1:32
;     WDTCPS = WDTCPS_1    Divider ratio 1:64
;     WDTCPS = WDTCPS_2    Divider ratio 1:128
;     WDTCPS = WDTCPS_3    Divider ratio 1:256
;     WDTCPS = WDTCPS_4    Divider ratio 1:512
;     WDTCPS = WDTCPS_5    Divider ratio 1:1024
;     WDTCPS = WDTCPS_6    Divider ratio 1:2048
;     WDTCPS = WDTCPS_7    Divider ratio 1:4096
;     WDTCPS = WDTCPS_8    Divider ratio 1:8192
;     WDTCPS = WDTCPS_9    Divider ratio 1:16384
;     WDTCPS = WDTCPS_10   Divider ratio 1:32768
;     WDTCPS = WDTCPS_11   Divider ratio 1:65536
;     WDTCPS = WDTCPS_12   Divider ratio 1:131072
;     WDTCPS = WDTCPS_13   Divider ratio 1:262144
;     WDTCPS = WDTCPS_14   Divider ratio 1:524299
;     WDTCPS = WDTCPS_15   Divider ratio 1:1048576
;     WDTCPS = WDTCPS_16   Divider ratio 1:2097152
;     WDTCPS = WDTCPS_17   Divider ratio 1:4194304
;     WDTCPS = WDTCPS_18   Divider ratio 1:8388608
;     WDTCPS = WDTCPS_19   Divider ratio 1:32
;     WDTCPS = WDTCPS_20   Divider ratio 1:32
;     WDTCPS = WDTCPS_21   Divider ratio 1:32
;     WDTCPS = WDTCPS_22   Divider ratio 1:32
;     WDTCPS = WDTCPS_23   Divider ratio 1:32
;     WDTCPS = WDTCPS_24   Divider ratio 1:32
;     WDTCPS = WDTCPS_25   Divider ratio 1:32
;     WDTCPS = WDTCPS_26   Divider ratio 1:32
;     WDTCPS = WDTCPS_27   Divider ratio 1:32
;     WDTCPS = WDTCPS_28   Divider ratio 1:32
;     WDTCPS = WDTCPS_29   Divider ratio 1:32
;     WDTCPS = WDTCPS_30   Divider ratio 1:32
;     WDTCPS = WDTCPS_31   Divider ratio 1:65536; software control of WDTPS
;
;   WDT operating mode:
; WDT lefagyasfigyelo uzemmodjanak megvalasztasa
;     WDTE = OFF           WDT Disabled; SWDTEN is ignored - Nincs engedelyezve fuggetlenul az SWDTEN-tol
;     WDTE = SWDTEN        WDT enabled/disabled by SWDTEN bit - Engedelyezest az SWDTEN bit hatarozza meg
;     WDTE = NSLEEP        WDT enabled while sleep=0, suspended when sleep=1; SWDTEN ignored
                                      ; WDT engedelyezve ha sleep=0, felfuggeszt ha sleep=1. SWDTEN hatastalan.
;     WDTE = ON            WDT enabled regardless of sleep - Engedelyezett, fuggetlenul az alvo uzemmodzol.
;
;   WDT Window Select bits:
;     WDTCWS = WDTCWS_0    window delay = 87.5; no software control; keyed access required
;     WDTCWS = WDTCWS_1    window delay = 75 percent of time; no software control; keyed access required
;     WDTCWS = WDTCWS_2    window delay = 62.5 percent of time; no software control; keyed access required
;     WDTCWS = WDTCWS_3    window delay = 50 percent of time; no software control; keyed access required
;     WDTCWS = WDTCWS_4    window delay = 37.5 percent of time; no software control; keyed access required
;     WDTCWS = WDTCWS_5    window delay = 25 percent of time; no software control; keyed access required
;     WDTCWS = WDTCWS_6    window always open (100%); no software control; keyed access required
;     WDTCWS = WDTCWS_7    window always open (100%); software control; keyed access not required
;
;   WDT input clock selector:
;     WDTCCS = LFINTOSC    WDT reference clock is the 31.0 kHz LFINTOSC
;     WDTCCS = MFINTOSC    WDT reference clock is the 32kHz MFINTOSC output
;     WDTCCS = SOSC        WDT reference clock is SOSC
;     WDTCCS = SC          Software Control
;
;   Boot Block Size selection bits:
;     BBSIZE = BBSIZE_8192 Boot Block size is 8192 words
;     BBSIZE = BBSIZE_4096 Boot Block size is 4096 words
;     BBSIZE = BBSIZE_2048 Boot Block size is 2048 words
;     BBSIZE = BBSIZE_1024 Boot Block size is 1024 words
;     BBSIZE = BBSIZE_512  Boot Block size is 512 words
;
;   Boot Block enable bit:
;     BBEN = ON            Boot block enabled
;     BBEN = OFF           Boot block disabled
;
;   Storage Area Flash enable bit:
;     SAFEN = ON           SAF enabled
;     SAFEN = OFF          SAF disabled
;
;   Application Block write protection bit:
;     WRTAPP = ON          Application Block write protected
;     WRTAPP = OFF         Application Block not write protected
;
;   Configuration Register Write Protection bit:
;     WRTB = ON            Configuration registers (300000-30000Bh) write-protected
;     WRTB = OFF           Configuration registers (300000-30000Bh) not write-protected
;
;   Boot Block Write Protection bit:
;     WRTC = ON            Boot Block (000000-0007FFh) write-protected
;     WRTC = OFF           Boot Block (000000-0007FFh) not write-protected
;
;   Data EEPROM Write Protection bit:
;     WRTD = ON            Data EEPROM write-protected
;     WRTD = OFF           Data EEPROM not write-protected
;
;   SAF Write protection bit:
;     WRTSAF = ON          SAF Write Protected
;     WRTSAF = OFF         SAF not Write Protected
;
;   Low Voltage Programming Enable bit:
;     LVP = OFF            HV on MCLR/VPP must be used for programming
;     LVP = ON             Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored
;
;   PFM and Data EEPROM Code Protection bit:
;     CP = ON              PFM and Data EEPROM code protection enabled
;     CP = OFF             PFM and Data EEPROM code protection disabled
;